1. Field of the Invention
This invention relates to a level shift circuit used to operate, particularly, turn on/off operation objects of semiconductor devices or electronic circuit devices of MOS transistors, insulated bipolar gate transistors, bipolar transistors, etc., receiving a power supply voltage on the high-voltage side according to input signals on the low-voltage side.
2. Description of the Related Art
The semiconductor devices and electronic circuit devices as the operation objects need to be operated under a power supply voltage appropriate for their respective applications. Since a control system for them normally is built in an integrated circuit operating under a low power supply voltage of about 5 V, it is difficult to directly control the operation objects by output of the control system. Thus, it is necessary to place a level shift circuit to which the invention is applied between the control system and the operation object and usually the level shift circuit is built in the integrated circuit for the control system. FIGS. 1 and 2 show; examples of conventional level shift circuits fitted to the purpose.
FIG. 1 shows a circuit for operating a power MOS transistor 101 of an operation object indicated in the upper right corner of the figure by an input signal Si at a low voltage of 5-15 V shown in the lower left corner of the figure when the MOS transistor 101 operates upon reception of 300-V power supply voltage VH, for example. A drive circuit 102 of a gate of the MOS transistor 101 is provided and to operate the drive circuit 102 on the high-voltage side, for example, a 15-V floating power supply (not shown) is connected to the power supply voltage VH. The MOS transistor 101 is provided for driving a load 103 on/off.
The level shift circuit is made up of a transistor 104 for receiving the input signal Si and a voltage dividing circuit consisting of a pair of resistors 105 and 106 connected between the transistor 104 and the power supply voltage VH for turning on/off the MOS transistor 101 through the drive circuit 102 by dividing voltage by the voltage dividing circuit. When the input signal Si is high and the transistor 104 is turned on, an electric current flowing from the power supply voltage VH side causes a voltage drop to occur in the resistor 105 and the voltage drop is given to the drive circuit 102. The drive circuit 102 normally consists of a plurality of inverter stages and when receiving the voltage drop in the resistor 105 as an operation, voltage, turns on the MOS transistor 101, for example. A Zener diode 107 connected to the resistor 105 in parallel is provided to always hold the operation voltage constant and prevent an overvoltage from being applied to the input of the drive circuit 102.
In a conventional example in FIG. 2, an operation object 101 is operated. The operation object 101 is a CMOS circuit operating upon reception of high-voltage side power supply voltage VH of about 15 V by a low-voltage input signal Si of about 5 V at TTL level. Since the high-voltage side power supply voltage VH is by far lower than that in FIG. 1, the floating power supply for a drive circuit 102 is omitted. The conventional level shift circuit consists of a pair of operation circuits 110 and 120 comprising high-voltage transistors 111 and 121 and low-voltage transistors 112 and 122 connected in series for receiving the high-voltage side power supply voltage VH.
As shown in the figure, the input signal Si is given to the low-voltage transistor 112 of the operation circuit 110; a complementary signal to the input signal Si by an inverter 160 operating upon reception of 5-V low-voltage side power supply voltage VL is given to the low-voltage transistor 122 of the operation circuit 120. The high-voltage transistor 121 of the operation circuit 120 is controlled according to the potential at the interconnection point between the transistors 111 and 112 of the operation circuit 110. The high-voltage transistor 111 of the operation circuit 110 is controlled according to the potential at the interconnection point between the transistors 121 and 122 of the operation circuit 120. The drive circuit 102 of the operation object 101 is operated according to the potential at the interconnection point on the side of the operation circuit 120.
When the input signal Si is low, the low-voltage transistor 112 of the operation circuit 110 is turned off, but the low-voltage transistor 122 of the operation circuit 120 is turned on, whereby the high-voltage transistor 111 of the operation circuit 110 is turned on, whereby the high-voltage transistor 121 of the operation circuit 120 is turned off. Thus, the drive circuit 102 receives the same low operation voltage as the input signal Si. When the input signal makes the low-to-high state transition, the on/off state of each transistor of the operation circuits 110 and 120 is inverted and the drive circuit 102 receives high operation voltage. As understood from this, in the conventional example in FIG. 2, the on/off state of the high-voltage transistor becomes opposite to that of the low-voltage transistor in the stationary state, thus a current flows into neither the operation circuit 110 nor 120. A current flows only in the transient state just after the high-to-low or low-to-high state transition of the input signal Si is made, and the operation voltage that the drive circuit 102 of the operation object 101 receives is switched high/low.
However, the conventional level shift circuits as discussed above involve the following problems: In the conventional example in FIG. 1, the electric power consumed by the level shift circuit becomes easily large because of the tradeoffs with the operation speed for the operation object 101. That is, when the-transistor 104 in FIG. 1 is turned on, power consumption, the product of current flowing into the transistor 104 via the voltage dividing resistors 105 and 106 and the high-voltage side power supply voltage VH, occurs. To decrease the power consumption, the resistance value of the resistors 105 and 106 may be raised for decreasing the current. However, the operation speed for the operation object 101 is restricted by a time constant, the product of the electrostatic capacity on the input side of the drive circuit 102 and the resistance value of the resistor 105. To provide a desired operation speed, the resistance value of the resistor 105 needs to be set to a predetermined limit or less. This also applies to the resistor 106 forming a part of the voltage dividing circuit like the transistor 105. Therefore, the power consumption of the level shift circuit can be decreased only to one limit and moreover increases rapidly as the high-voltage side power supply voltage VH.
In contrast, in the conventional example in FIG. 2, a current flows into the operation circuits 110 and 120 of the level shift circuit only at the beginning of the logic state transition of the input signal Si, as described above, so that power is by far less consumed than that in the example in FIG. 1. If the high-voltage side power supply voltage VH becomes several ten V or more, the circuit as in FIG. 2 cannot deal with it, but this problem can be solved if power is supplied to the drive circuit 102 from a floating power supply, such as described with regard to FIG. 1. However, the test result of operating the level shift circuit revealed that the operation speed for the operation object 101 cannot much be increased.
That is, to increase the operation speed, the electrostatic capacity on the input side of the drive circuit 102 needs to be charged and discharged rapidly. To do this, first the on resistance of the transistors 121 and 122 of the operation circuit 120 must be decreased and it is desirable that the on resistance of the transistors 111 and 112 of the operation circuit 110 are also decreased. However, if the on resistance is decreased, a so-called through current transiently flowing into the operation circuits 110 and 120 at the state transition time of the input signal Si increases. If the time for which the through current flows is prolonged due to component transistor operation time variations, etc., transistor destruction or characteristic degradation become prone to occur. As a result in the conventional example in FIG. 2, the operation speed for the operation object 101 can be increased only in a safety range in which such trouble can be prevented from occurring.
Subsequently, another conventional example will be described which shows a level shift circuit (level shifter) for converting an input signal of narrow logic amplitude in a 3-V range, for example, into an output signal of wide logic amplitude in a 30-V range, for example.
For example, a level shift circuit for converting a selection signal at a low voltage level into a liquid crystal drive voltage at a high voltage level is built in a liquid crystal drive IC (liquid crystal driver) in addition to a power transistor at an output stage. Hitherto, the basic form of this level shift circuit has been a flip-flop circuit configuration of low power consumption type wherein two stages of CMOS are connected for applying feedback, as shown in FIG. 3. That is, a level shift circuit 10 shown in FIG. 3 has a CMOS inverter INV1 for generating, for example, from a logic input signal VIN of narrow logic amplitude (3 V=Vdd-Vss) produced by a power supply in a 3-V range (0 V (=Vss) to 3 V (=Vdd)) power supply, an inverted signal VIN* of opposite phase in the 3-V range, a first n-channel MOSFET (first switch MOS) l for pull down, opened/closed by the logic input signal VIN, a second n-channel MOSFET (second switch MOS) 2 for pull down, opened/closed by the inverted signal VIN* exclusively with the first n-channel MOSFET 1, a first p-channel MOSFET 3 connected to the first n-channel MOSFET 1 in a totem-pole manner (in series) between 30-V (0 V (Vss) to 30 V (Vcc)) high-voltage power supplies, for example, and closed as the second n-channel MOSFET 2 is closed, and a second p-channel MOSFET 4 connected to the second n-channel MOSFET 2 in a totem-pole manner between 30-V (0 V (Vss) to 30 V (Vcc)) power supplies and closed as the first n-channel MOSFET 1 is closed.
The first p-channel-MOSFET 3 and the second p-channel MOSFET 4 make up a flip-flop FF with drain nodes (storage nodes) N1 and N2 cross-connected to mutual gates. Here, an output signal Vout of wide logic amplitude of the level shift circuit 10 is taken out from the drain node N2 and its inverted output signal Vout* appears at the drain node N1.
In the level shift circuit 10 of the basic configuration, when the logic input signal VIN rises from low level 0 V (=Vss) of narrow logic amplitude to high level 3 V (=Vdd), the first n-channel MOSFET 1 is closed, and as the inverted signal VIN* of opposite phase falls to 0 V (=Vss), the second n-channel MOSFET 2 is opened. As the first n-channel MOSFET 1 is closed, 0 V (=Vss) is fed into the drain node N1 of the flip-flop FF and the voltage is defined as low level of wide logic amplitude. As the second n-channel MOSFET 2 is opened, the voltage of the drain node N2 floats and becomes once undefined. However, the second p-channel MOSFET 4 is closed according to the defined voltage 0 V of the node N1. Thus, the drain node N2 immediately is defined as high-level voltage 30 V (=Vcc) of wide logic amplitude. As a result, the first p-channel MOSFET 3 is opened. Thus, a p-channel MOSFET 5 at an output stage with its gate connected to the drain node N2 is opened.
In contrast, when the logic input signal VIN falls from high level 3 V (=Vdd) to low level 0 V (=Vss), the first n-channel MOSFET 1 is opened and the second n-channel MOSFET 2 is closed. 0 V (=Vss) is fed into the drain node N2 of the flip-flop FF and the voltage is defined as low level of wide logic amplitude. The voltage of the drain node N1 floats and becomes once undefined. However, the first n-channel MOSFET 3 is closed according to the defined voltage 0 V of the node N2. Thus, the drain node N1 immediately is defined as high-level voltage 30 V (=Vcc) of wide logic amplitude. As a result, the second p-channel MOSFET 4 is opened. Thus, the p-channel MOSFET 5 at the output stage with is closed.
Thus, the level shift circuit 10 provides the step waveform of the logic output signal VOUT of wide logic amplitude of low level 0 V (Vss) to high level 30 V (Vcc) with respect to the step waveform of the logic input signal VIN of narrow logic amplitude of narrow logic amplitude of low level 0 V (Vss) to high level 3 V (Vdd).
The level shift circuit 10 is made monolithic as a semiconductor integrated circuit (IC) together with a preceding-stage circuit (not shown) for generating the logic input signal VIN and the MOSFET 5 at the output stage. Thus, it is desirable to form the gate insulting films of the MOSFETs in one chip all as the same thickness from cost merits by reducing the manufacturing process steps. However, since the potentials of the drain nodes (storage nodes) N1 and N2 of the flip-flop FF in the level shift circuit 10 are reset to 0 V (Vss) alternately as the switch MOSs 1 and 2 are opened and closed. Thus, the source-to-drain voltage becomes a high voltage (about 30 V) in the first and second p-channel MOSFETs 3 and 4 making up the flip-flop FF and the MOSFET 5 at the output stage. Thus, transistors of a high voltage resistance structure formed with a low-concentration drain region of offset gate type are required. Further, since high voltage (about 30 V) is also applied between gate and source, between gate and drain, and between gate and substrate, the gate insulating films of the MOSFETs 3 to 5 must be formed furthermore thick as compared with those of MOSFETs of other low-voltage control circuits for the purpose of improving the gate voltage resistance.
A level shift circuit 20 shown in FIG. 4 is proposed in order to place the gate-to-source voltage resistance, gate-to-drain voltage resistance, and gate-to-substrate voltage resistance within 3-V voltage resistance. That is, the level shift circuit 20 has a configuration wherein in the level shift circuit 10 shown in FIG. 3, the gates of the first and second p-channel MOSFETs 3 and 4 making up the flip-flop FF are connected to 30-V (Vcc) high-voltage power supply via voltage regulation diodes D1 and D2 for diode clamper.
Assuming that the Zener voltage Vz of these voltage regulation diodes D1 and D2 is about 3 V, if the first n-channel MOSFET 1 is closed, the drain node N1 does not fall below Vcc-Vz=about 27 V because of voltage clamp of the voltage regulation diode D2, and the gate-to-source, gate-to-drain, and gate-to-substrate voltages of the second p-channel MOSFET 4 are placed within 3 V. Likewise, if the second n-channel MOSFET 2 is closed, the drain node N2 does not fall below about 27 V either because of voltage clamp of the voltage regulation diode D1, and the gate-to-source, gate-to-drain, and gate-to-substrate voltages of the first p-channel MOSFET 3 are placed within 3 V. The gate-to-source and gate-to-substrate voltages of the MOSFET 5 at the output stage are also placed within 3 V. The gate voltage resistance of the MOSFET 5 at the output stage as well as the MOSFETs 3 and 4 of the flip-flop FF needs only to be 3-V voltage resistance. Since 3 V or more is applied as the source-to-drain voltages of the switch MOSs 1 and 2 and the MOSFET 5 at the output stage, high-voltage resistance MOSFETs of an offset gate structure, etc., having a low-concentration drain region (circled in FIG. 4) are used for the MOSFETs 1, 2, and 5.
By the way, in the level shift circuit 10 shown in FIG. 3, in the stable (stationary) state of the flip-flop FF, current is not consumed on the principle except leakage current of the switch MOS 1 or 2 (saturation current of p-channel MOSFET 3 or 4), and only a minute through current flows into a 2-stage series circuit in the transition process of the flip-flop FF. Therefore, low power is consumed. On the other hand, in the level shift circuit 20 shown in FIG. 4, in the process in which the first switch MOS 1 is closed, the current which should be allowed to flow into the first switch MOS 1 is such a breakdown current to cause Zener voltage Vz to occur in the diode D2 more than the saturation current flowing into the first p-channel MOSFET 3 closed in the immediately preceding stable state (write current for placing the storage node N1 in low level), and in the process in which the second switch MOS 2 is closed, the current which should be allowed to flow into the second switch MOS 2 is equal to or greater than the sum of such a breakdown current to cause Zener voltage Vz to occur in the diode D1 more than the saturation current flowing into the second p-channel MOSFET 4 closed in the immediately preceding stable state (write current for placing the storage node N2 in low level) and a charge current to charge source-to-gate capacity (gate capacity) C5 of the p-channel MOSFET 5 at the output stage. After the first switch MOS 1 shifts to the stable state of the closed state of the MOS 1, the current which should be allowed to flow into the first switch MOS 1 may be a minute current (hold current) sufficient for the diode D2 to hold the Zener voltage Vz. After the second switch MOS 2 shifts to another stable state of the closed state of the MOS 2, the current which should be allowed to flow into the second switch MOS 2 may be a minute current (hold current) sufficient for the diode D1 to hold the Zener voltage Vz.
However, in the circuit configuration in FIG. 4, after the first switch MOS 1 reaches the stable state of the flip-flop FF of the closed state, the current of the same value as that at the state transition time of the MOS 1 still continues to flow into the first switch MOS 1, and after the second switch MOS 2 reaches another stable state of the flip-flop FF of the closed state, the current of the same value as that at the state transition time of the MOS 2 still continues to flow into the second switch MOS 2. Thus, large power is consumed.
Then, the present applicant proposes a level shift circuit 30 comprising drain current variable circuits 32 and 34 shown in FIG. 5. This level shift circuit 30 has source resistors R11 and R12 in series making up a source follower circuit (constant current circuit) together with the first n-channel MOSFET 1 operating in a non-saturation region, an n-channel MOSFET 6 for changing source resistance value for short-circuiting the source resistor R12, a one-shot circuit (monostable multivibrator) 7 for applying a change time limit pulse P1 of predetermined pulse width .DELTA.T1 to a gate of the MOSFET 6 at time t1 at which logic input signal VIN rises, source resistors R21 and R22 in series making up a source follower circuit (constant current circuit) together with the second n-channel MOSFET 2 operating in a non-saturation region, an n-channel MOSFET 8 for changing source resistance value for short-circuiting the source resistor R22, and a one-shot circuit 9 for applying change time limit pulse P2 of predetermined pulse width .DELTA.T2 (=.DELTA.T1) to a gate of the MOSFET 8 at time t2 at which logic input signal VIN falls, in the level shift circuit 20 shown in FIG. 4.
The first n-channel MOSFET 1, the source resistors R11 and R12, the n-channel MOSFET 6 for changing source resistance value, and the one-shot circuit 7 make up the first drain current variable circuit 32. The second n-channel MOSFET 2, the source resistors R21 and R22, the n-channel MOSFET 8 for changing source resistance value, and the one-shot circuit 9 make up the second drain current variable circuit 34.
At the time t1 of the state transition process of the flip-flop FF at which the logic input signal VIN rises, the MOSFET 6 is held closed only for the .DELTA.T1 time as the change time limit pulse P1 occurs. Thus, only the resistor R11 serves as the source resistors of the first n-channel MOSFET 1, causing drain current ID1 flowing into the first n-channel MOSFET 1 to increase rapidly. After the expiration of the .DELTA.T1 time, the MOSFET 6 is opened and the resistor R12 is connected to the resistor R11 in series, thus the drain current ID1 flowing into the first n-channel MOSFET 1 is decreased rapidly and is restored to a minute current. At the time t2 of another state transition process at which the logic input signal VIN rises, the MOSFET 8 is held closed only for the .DELTA.T2 time as the change time limit pulse P2 occurs. Thus, only the resistor R21 serves as the source resistors of the second n-channel MOSFET 2, causing drain current ID2 flowing into the second n-channel MOSFET 2 to increase rapidly. After the expiration of the .DELTA.T2 time, the MOSFET 8 is opened and the resistor R22 is connected to the resistor R21 in series, thus the drain current ID2 flowing into the second n-channel MOSFET 2 is decreased rapidly and is restored to a minute current. Thus, the drain currents ID1 and ID2 of the first and second n-channel MOSFETs become each rapidly increased drain current IMAX in the transition process of the flip-flop FF and power-saving drain current (static mode current) IMIN in the stable state, thus contributing to the reliable state transition and reduction in power consumption.
By the way, if the level shift circuit 30 in FIG. 5 is viewed as a dynamic circuit, in the configuration in which the power p-channel MOSFET 5 at the output stage is connected to either of drain nodes N1 and N2 of the flip-flop FF, the large source-to-gate capacity C5 can be assumed to be connected to one of the nodes. Thus, the scale of the elements and signal change timing symmetry in the level shift circuit 30 are lost inevitably.
That is, as shown in FIG. 5, when the gate of the p-channel MOSFET 5 at the output stage is connected to the drain node N2, if the first n-channel MOSFET 1 is closed at the time t1 and the second n-channel MOSFET 2 is opened, the second p-channel MOSFET 4 is closed. This second p-channel MOSFET 4 is built in, the chip as a comparatively large-scale element to rapidly discharge the source-to-gate capacity C5. Thus, it is a large element as compared with the first p-channel MOSFET 3 and a source-to-gate capacity C4 that cannot be ignored is parasitic on the second p-channel MOSFET 4 inevitably.
As a result, if the second n-channel MOSFET 2 is closed at the time t2 at which the logical input signal VIN falls and the first n-channel MOSFET 1 is opened, the voltage of the drain node N1 is hard to rise because of the source-to-gate capacity C4 at the beginning and the second n-channel MOSFET 2 still remains closed. Thus, almost all of the rapidly increased drain current IMAX flowing into the second n-channel MOSFET 2 at the state transition time passes through the second p-channel MOSFET 4 as a reactive current and is hard to flow through the voltage regulation diode D1 and on resistance of the second n-channel MOSFET 2 of comparatively large element scale is low. Therefore, falling of the gate voltage of the first p-channel MOSFET 3 (voltage of drain node N2) is delayed. Thus, the MOSFET 3 is closed after a time lag and Vcc voltage it is supplied to the node N2. However, the gate voltage of the second p-channel MOSFET 4 does not immediately rise because of the discharge time of the source-to-gate capacity C4, and is opened behind the time at which the second n-channel MOSFET 2 is closed.
As shown in FIG. 6, the rapidly increased drain current IMAX flows as a reactive current Q1 at the time interval between the time t2 at which the logic input signal VIN falls and the second n-channel MOSFET 2 is closed and the time t21 at which the second p-channel MOSFET 4 is opened. Likewise, the rapidly increased drain current IMAX also flows as a reactive current q1 at the time interval between the time t1 at which the logic input-signal VIN rises and the first n-channel MOSFET 1 is closed and the time t11 at which the first p-channel MOSFET 3 is opened. However, since the gate capacity of the first p-channel MOSFET 3 can be ignored, the time interval between the time t1 and the time t11 is fairly short as compared with the time interval between the time t2 and the time t21 and the reactive current q1 is also fairly short as compared with the reactive current Q1.
When the opening time of the second p-channel MOSFET 4, t21, is reached, all the rapidly increased drain current IMAX flowing into the second n-channel MOSFET 2 at the state transition time flows effectively through the voltage regulation diode D1, thus the voltage of the drain node N2, VOUT, falls by Zener voltage VZ from the power supply voltage Vcc and charging of the source-to-gate capacity C5 is first started.
Although short-circuit discharge is a moment as the second p-channel MOSFET 4 is closed, the source-to-gate capacity C5 is charged (charge amount Q2) with a comparatively large time constant corresponding to the product of the large capacity C5 and resistance of the source follower circuit containing the second n-channel MOSFET 2. Thus, the voltage of the drain node N2, namely, the output signal VOUT falls moderately in an exponential waveform. As a result, the turn-on time of the p-channel MOSFET 5 at the output stage, TON, is prolonged and is unbalanced with the turn-off time TOFF; the p-channel MOSFET 5 at the output stage has a poor switching characteristic.
To resolve the imbalance between the turn-on time TON and the turn-off time TOFF, the element area of the second n-channel MOSFET 2 itself can be formed on a large scale as compared with the first n-channel MOSFET 1 for increasing the current capacity to further increase the rapidly increased drain current IMAX flowing into the second n-channel MOSFET 2 at the state transition time to rapidly charge the source-to-gate capacity C5 from the time t21. This leads to an increase in the chip size, causing the cost of manufacturing a semiconductor integrated circuit to rise. In addition, the following imperfections on the operation can be pointed out:
(1) If the current capacity of the second n-channel MOSFET 2 itself is increased for rapidly charging the source-to-gate capacity C5 as described above, charging of the gate capacity C5 is not started until the opening time of the second p-channel MOSFET 4, t21, is reached. Thus, the turn-on time is made longer than the turn-off time by the charge time interval t21-t23, and the switching speed is slow. PA1 (2) If furthermore large rapidly increased drain current IMAX' (&gt;IMAX) is caused to flow into the second n-channel MOSFET 2 at the state transition time, as shown in FIG. 6, to rapidly charge the source-to-gate capacity C5 of the p-channel MOSFET 5 at the output stage, the rapidly increased drain current IMAX' must be previously allowed to flow as a further large current through 2-stage series circuit (reactive current) Q1' at the time interval between the time at which the second n-channel MOSFET 2 is closed (the logic input signal VIN rises), t2, and the time at which the second p-channel MOSFET 4 is opened, t21. Thus, the reactive current increases and power consumption grows. PA1 (3) Because of current value variable circuit of time limit change type, the time limit for changing from the rapidly increased drain current IMAX to the power-saving drain current IMIN (time t11, time t23) depends uniformly on the pulse width .DELTA.T1, .DELTA.T2 of the change time limit pulse P2 by the one-shot circuit 7, 9. If the pulse width is too short, a change is made to the decreased drain current IMIN before the voltage of the node N1, N2 rises or falls sufficiently. As a result, the rising or falling is further delayed and the transition time (turn-on time, turn-off time) is prolonged. If the pulse width is too long, the rapidly increased drain current IMAX continues to flow unnecessarily still after the voltage of the node N1, N2 rises or falls sufficiently, thus power consumption increases. In fact, however, variations in element characteristics, temperature characteristic, etc., must be considered to set the pulse width .DELTA.T1, .DELTA.T2 on the long side. Therefore, power consumption grows at the state transition time.
Before it, a time lag occurs by the time the second p-channel MOSFET 4 is opened because of the source-to-gate capacity C4 parasitic on the second p-channel MOSFET 4. Thus, the turn-on time is prolonged as long as the time lag as compared with the turn-off time and is unbalanced with the turn-off time.
Therefore, a trade-off exists between improvement in the switching speed by shortening the turn-on time in (1) above and reduction in the reactive current at the state transition time.